1. Field of the Invention
The present invention relates to a clock monitoring circuit for detecting that the period of a clock signal has become shorter than a predetermined permissible range.
2. Description of the Related Art
Processors that operate in synchronization with a clock signal generated by a clock generating circuit and that execute various types of processing are currently implemented, for example, in the form of MPUs (Micro Processing Units). Processors such as MPUs are designed to operate in synchronization with a clock signal of a predetermined period and are therefore subject to overrunning when the period of this clock signal has become shorter than the predetermined period.
It is an object of the present invention to provide a clock monitoring circuit that can easily and accurately detect that the period of a clock signal has become shorter than a predetermined period.
It is another object of the present invention to provide a data processing device that is equipped with the above-described clock monitoring circuit and that can prevent overrunning of a processing circuit when the period of the clock signal has become shorter than the predetermined period.
In order to achieve the above-described objects, the clock monitoring circuit of the present invention comprises first and second flip-flop circuits, a delay means, and a gate circuit. The first and second flip-flop circuits are D-type flip-flops that latch input signals in synchronization with the rising edge or falling edge of a clock signal.
The second flip-flop circuit receives as an input signal the output signal of the first flip-flop circuit. The output signal of the second flip-flop circuit is delayed a fixed time period by the delay means and then supplied as an input signal to the first flip-flop circuit. The delay time of the delay means is set to be equal to the previously described predetermined period.
The gate circuit is constructed such that it receives the output signals of the first and second flip-flop circuits and provides an output signal whose logic level depends on whether the period of the input clock signals is the predetermined period or not. A shortening of the period of the clock signal can thus be detected according to the logic level of the output signal of the clock monitoring circuit.
A data processing device according to the present invention includes the aforementioned clock monitoring circuit. When an abnormality in the clock signal is detected by the clock monitoring circuit, this abnormality is communicated to an operation control circuit that controls the operation of the processor, halting the operation of the processor.
Overrunning in the processing circuit due to abnormalities of the clock signal can thus be stopped.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings, which illustrate examples of the present invention.